Research On CMP Architecture Based On Resource Optimization

The development of the Ultra Deep Sub Micron technique brings the integrated circuit to a new epoch of VLSI. The efficient utilization of the increased transistors in a single chip is a hot field of computer architecture researches. Owing to the advantages of high thread level parallelism, simple control logic, high main frequency and the short period of design and verification, CMP has been considered as the inevitable trend of the future processor architecture development.On the basis of the CMP architecture and the correlative technologies, a two-level resource optimization architecture based on CMP architecture with SMT cores is proposed. The two-level resource optimization architecture consists of the inter-core thread dynamic transfer structure and the inner-core thread selection and instruction fetch structure. The inter-core thread dynamic transfer optimizes the utilization of the whole processor resource through balancing the thread workload among each processor cores by the thread dynamic transfer. And the inner-core thread selection and instruction fetch reduces the instruction block efficiently and increases the effective resource utilization inside the processor core through controlling the thread selection and the instruction fetch by the priority strategy.Based on the analysis of the existed SMT simulator, a CMP simulator for this two-level resource optimization architecture has been designed and the roundly performance tests have been done for this two-level architecture. The results of the tests manifest that the two-level resource optimization architecture can improve the system performance greatly.