VLSI Design Of Full-Search Block-Matching Full-Pel Motion Estimation For H.264

H.264 is the newest video coding standard, which was drafted by the JVT (Joint Video Team) of ITU-T VCEG and ISO/IEC MPEG in March, 2003. Many applications such as wireless mobile video communication of low bandwidth, high error code rate and video broadcast & online multimedia of high code rate, low latency are supported by H.264, and it is being hot attention. Many new features are used in H.264 for higher coding efficiency, especially the quarter-sample-accuracy, variable block-size and multiple reference frames for motion estimation and compensation. So H.264 is more than twice encode performance comparing with MPEG-2 and H.263 in the same decoding image quality. However, the computation complexity increases much more, and much time and system resource are consumed. Motion estimation can consume 60% to 80% of the total encoding time, and full-pel motion estimation consumes most of it. In order to get real time performance and achieve huge computation task, hardware speedup is needed and parallel processing must be exploited in the architecture.Based on the features of high performance VLSI design and the research of many algorithms and architectures of full-pel motion estimation, an improved variable block size full-search block-matching motion estimation architecture, which is 16×16 systolic array, is proposed. The VLSI design is also achieved. Data reuse is taken into account in this design. Reference frame data are stored into the on chip RAMs and the search area data of different RAMs are not needed to be transferred between each other.The current frame data are reused and moved horizontally and vertically in the PE array. The one-access architecture is able to be 100% utilized via a suitable data loading sequence, and the data bandwidth is decreased sharply. The search area is 16×16 and one block matching is finished per clock cycle. Variable block size motion estimation is achieved by reuse and combination of small block SAD. The algorithm was verified by Matlab. The proposed architecture was designed with Verilog and synthesized by Synopsys Design Compiler with HJTC 0.18μm 1P6M CMOS technology. The clock frequency is 125MHz, and the equivalent area is 208K logic gates and 30K bytes SRAM. Layout is designed by Cadence SoC Encounter and the chip area is 4mm×4mm. Experimental results show that it is able to finish the full-pel motion estimation of Supper HDTV video sequences (1920×1080, 60f/s) in real-time, and meet the application of H.264.