Research And Efficient Design Of Elliptic Curve Cryptograph Over GF(2~m)

With the rapid development of computers and the Internet, information security has received increasing attention. The core of information security is the cryptographic technique. As a new public-key cryptosystem with a short key, Elliptic Curve Cryptosystem (ECC) is characterized as fast implementation and high security, which has a wide range of potential applications. This paper leads a comprehensive study about the various algorithms and hardware perspectives of the elliptic curve, provides a practical and efficient hardware implementation for ECC algorithm, and addresses the methods of improving the security issue.Elliptic Curve Cryptosystem has complicated mathematical background, covering a wide range of algorithms. Based on the in-depth analysis of Elliptic Curve mathematical algorithm and Elliptic Curve Cryptosystem, we have proposed a hardware implementation of ECC. The implementation of operators for modular multiplication over the Finite Fields adopts an improved serial structure, considering the trade-off between size and speed. After comparison with the two modular inverse algorithms, we selected the extended Fermat method from the perspective of improving performance. Considering the diversity of the ECC algorithm, we did not directly adopt the fast algorithm targeting a specific curve when searching the efficient implementations. The kP scalar multiplication on Elliptic curves group is the most important operation. Due to the characteristics of finite field operations of ECC at the bottom level, we finally chose the projection coordinates of DA methods for fast hardware implementation by using the finite state machine. On the basis of timing attacks analysis theory, a hardware countermeasure by using random variable to mask timing characteristics is presented to enhance the security of the design.In this paper, we build an experimental environment by using Verilog HDL as a hardware description language, EDA tools and C language programs for logic simulation, synthesis and verification. The detailed verification process and simulation results are given. The results show that the proposed design can meet our prospective requirements of ECC.