Design Of The USB Engine In The Flow Meter SOC Chip

Possessing the advantages of high speed, easy to connect, no need of external power and the favorable compatibility, The USB interface has already become the prior choice for many peripheral devices to connect with the computer.The flow meter SOC chip uses the USB interface to complete the measure results reading and configuration adjusting by the computer. This paper mainly focuses on the design of the USB engine in this SOC chip, which is the key part of the USB interface. Based on study of the system requirements, The SIE and the management unit for three endpoints are designed to support the USB controlling and bulk communication. Also a user-enable enumeration processor is designed to deal with the USB enumeration process, which can simplify the MCU program as well as to improve the enumeration speed.The whole design follows the ASIC design flow. Based on system study, the design is divided into several small and manageable modules. Starting with the RTL design using the verilog HDL, the simulation and the Cyclone EP1C12Q240C8 based FPGA verification was carried out to prove that the design had reached the expected goal. Considering the Design-For-Test requirements, the RTL code was synthesized by DFT Compiler using the Chartered 0.35μm process standard cell library; the circuit is optimized and the full-scan chain is built. The EDA tool Primetime and Formality are used respectively to analyze the static timing and compare the gate netlist with the verified RTL code, to make sure that the synthesized circuit is functionally right. Finally the layout is obtained using the APR tool Astro. The post-simulation and static timing analysis using the standard delay file demonstrate that the physical layout has no timing violations and the circuit has realized the function, consistent with the USB1.1 protocol, it supports the USB communication based on controlling and bulk transfer. In the design, the DFT method is adopted, by building full-scan configuration in the circuit, the fabricated faults can be conveniently tested. In this way, the USB engine can be towardly designed into a reusable IP core.