A VLSI Implementation Of EBCOT Encoder For JPEG2000

JPEG2000 is the next generation digital still image compression standard introduced by JPEG (Joint Photographic Experts Group) in December, 2000. JPEG2000 provides not only superior compression performance over JPEG, but also provides a rich set of features, in answer to the ever growing requirements for image coding techniques.However, these advantages come at the price of much higher computation complexity, especially in the EBCOT Tier-1 coding algorithm. The two main components in EBCOT Tier-1,the bit-plane coding and context-based adaptive binary arithmetic coding algorithm each involves considerable bit-level operations and complex control, therefore becomes the processing bottleneck of the entire JPEG2000 encoding system.So, high-speed, low-power, application-specific hardware implementation of EBCOT Tier-1 encoder with reasonable area is of has fundamental importance for application of the JPEG2000 standard.This thesis gives a research on the bit-plane coding and MQ arithmetic coding algorithm of EBCOT Tier-1. By analyzing the existing hardware implementation schemes, a bit-plane-parallel and pass-parallel coding VLSI architecture is proposed ,a three-pipelined VLSI architecture adapted to bit plane-parallel and pass-parallel coding is designed,finally, an optimized MQ scheme based on pipelined is proposed.Our proposed design outperforms the other exisiting design significantly.Our proposed EBCOT encoder architecture is applied to the efficient image compression system based on JPEG2000. The system could meet the demands of real time image processing, with the technical indices of 30 frames per second,1024 by 1024 pixels resolution,and 16 bits per pixel,etc.Through the exhaustive hardware and software assessment with a large number of images, the encoder stream output by our system is proved to aggree with the JPEG2000 standard.