Research On High-Level Synthesis Techniques For Low Power

AS the development of the manufacturing technology and the increase of the scale of integrated circuits, power consumption has emerged as one of the most important issues in the integrated circuit design. Traditional methods have been hard to resolve the low power problem encountered in circuit design, while high-level synthesis techniques may greatly optimize the power consumption of circuits. Different design levels lead to different power optimization abilities. There is huge space for power optimization at the high-level synthesis stage, whereas this space becomes much smaller when the circuit reaches the physical design stages. So, it can get better effects when considering power optimization problem at higher levels. High-level synthesis for low power is thus becoming a more and more important problem.In this thesis, we introduce some basic knowledge of high-level synthesis, and research feather the high-level optimization techniques for low power. Our work includes mainly the following two aspects:A modified high-level synthesis algorithm for dynamic power optimization is proposed. First, a dynamic power model considering time, resources and data-dependent constraints is established. Then, under time, resources and data-dependent constraints, dynamic power of the circuit can be minimized through resource scheduling and allocation in high-level synthesis using a hybrid algorithm combined genetic algorithm with ant colony algorithm. Experimental results on a number of benchmarks show that the proposed approach can significantly reduce the dynamic power consumption of circuits.A modified high-level synthesis algorithm for interconnect power optimization is proposed. First, a interconnect power model is devised, which estimates the interconnect power of a circuit through the transition activities on the bus lines. Then, given a scheduled dataflow graph to be synthesized, our algorithm binds the input data to the proper buses and adjusts the order of signal lines in each bus using the greedy algorithm to approximately minimize the total transition activity on the buses, which will reduce the interconnect power efficiently. Experimental results on a number of benchmarks demonstrates the superiority in reducing the interconnect power compared with the existing methods.