Design And Implementation Of Front-End DDS Based On ASIC Flow

Today, as the electronic technology is developing fantastically fast, higher performance of frequency synthesizer is put forward, wide frequency range, high frequency resolution, low jump time, low phase noise, high spurious restraining and controlled by program .These requirements are too hard to reached by using normal analog circuit. Therefore, how to design a new frequency synthesizer to produce a great deal of high resolution, high stabilization frequency signal has become the key technology of synthesis.In this paper, the basic theory of frequency synthesize is introduced firstly, compare and analyze all kinds of frequency synthesize technology to know its advantage and disadvantage, DDS mostly used in frequency synthesize is introduced in detail; Because this frequency synthesizer is based on ASIC, ASIC design flow and related technology is also introduced in this paper; Then, accounting to the design of Direct Digital Frequency Synthesizer(DDS) based on the flow of the Application Specific Integrated Circuits(ASIC),this text carried on system architecture and module partition and algorithmic analysis; As following, making use of the hardware description language Verilog HDL carried on the DDFS of the front of the RTL function simulation and the write of test-bench, the style of code and the Comprehensive and the high overlap of test-bench did cushion for the subsequent door class realization; Finishing all the designs on the digital part module, simulate until the whole process of timing analysis and synthesis optimization,which include the FPGA verification and ASIC implement,and the former one insures the latter one successfully carry on; The RTL simulation tool is as the Modelsim of Mentor company, the FPGA verification tool is as ISE of Xilinx company, the synthesis and static timing analyse tool is as the Design Compiler and Primetime of Synopsys company, adjusting to use craft database is UMC's 0.18μm; For satisfying the request of high frequency and low tremble a dynamic, needing to be synthesized again and again, and fully taking consider into all kinds of factors, such as speed and area; At last, for the application realm of the DDS, the part of digital modulation will be functionally tested and simulated.Accounting to the design and implement of the ASIC flow in this paper, finishing well on function and timing,area,power and so on,and also make the DDS module more transplant and reuse,which satisfy the IP core design condition and have fairly practical value.