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Design Of Fibre Channel Controller Based On SoPC And Implementation Of FC-2 Layer

Posted on:2008-05-08Degree:MasterType:Thesis
Country:ChinaCandidate:H G ChaiFull Text:PDF
GTID:2178360272468902Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
There are mainly two kinds of design technology in system-level chip designs, called SoC(System on Chip) and SoPC(System on Programmable Chip). SoC depends on ASIC(Application Specific Integrated Circuit), which brings high costs and long development cycle. SoPC based on PLD and overcomes the shortcomings of SoC, it's flexible and can be cut, expand, upgrade and have a certain ability of system programming. Fibre Channel is a high-speed, long distance and extensible transport protocol, it plays an important role in storage area. Developing Fibre Channel controller with SoPC can effectively play SoPC advantages for hardware and software customization and facilitate expansion. In light of the actual situation, the hardware and software co-design model is chosen as the development model of the system. The hardware part plays role of FC0, FC1 and part of FC2, the software part is divided into four modules, that's FC2 layer, FCP (Fibre Channel Protocol for SCSI)layer, login&discovery and resource management. FC2 layer mainly in charge of frame, sequence and exchange management. Modules ofFC2 communication with each others by queue. There are two kinds of queue in the system, they are link-list queue and array queue. As one queue may be accessed by multi modules, a protective mechanism is designed, the performance of the system should be considered when using mutex protection. When handling queue of full load must also considers the impact on system performance, different approach is taken according to the queue's position in system data flow. FC2 layer also in charge of communication with hardware part. Frame is transported between hardware and software according to DMA, the hardware informs the software through interrupt to read the frame out when a frame received. Constrains on interrupt has been adopted in order to enhance efficiency. System is divided into several functional components in order to achieve a fine-grained control. Centralized management and Time Processing are taken as the regular status monitoring and error processing Strategy. This will not only guarantee the normal operation of systems, but also allow the various components can concentrate on their own terms, speed up the process.The system performace can be enhanced by constructing multi-processes system and realization of hardware scatter/gather list.
Keywords/Search Tags:Fibre Channel, System on Programmable Chip, hardware and software co-design
PDF Full Text Request
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