Research And Optimization Of 10 Bit, 100 MS/s Analog-to Digital Converter

Typically, high-resolution ADCs are based on successive approximation or oversampling architectures, but both of these architectures can not attain high speed of conversion. The pipelined analog-to-digital converter (ADC) is a popular structure for high-speed and high-resolution data conversion and can attain compact area and efficient power dissipation.Applications such as high-end video signal processing, high performance digital communications, and medical imaging require ADCs with sample rates approaching 100 MS/s and a dynamic range at the Nyquist bandwidth close to 60 dB. In response to these needs, there is a continued search for architectures and circuit techniques enabling a monolithic ADC to meet these specifications with a reasonable chip area and power dissipation. It is of particular interest that if such an ADC is fabricated in a standard CMOS technology.This work addresses some of the known problems inherent in time-interleaved, or parallel, pipeline ADCs with a new architecture. A prototype of this architecture demonstrates, for the first time, 10-bit operation at the maximum sampling rate up to 95 MHz in 1μm CMOS technology. It attains 59.5 dB SNDR at a low conversion rate, and more than 50 dB SNDR at 50MHz input frequency with a 95 MHz conversion rate. By using a minor offset control to suppress the fs/2 tone, 65 dB spurious free dynamic range (SFDR) is achieved. The ADC implemented in fully differential circuitry uses the 2-channel 3-stage pipeline architecture. Each stage converts 4-bits, and 2-bits from 12-bit are used for digital error correction. The comparator schematic are deeply identified and analyzed for the sub-ADC in the parallel pipeline architecture. A optimized comparator is presented to release the requirement of high-speed and high-resolution parallel pipeline ADCs. Because all the digital clock signals are generated from the on-chip clock buffer, it requires a single full speed clock signal.