Research On FPGA Implementation Of A Multi-bit-plane Parallel Algorithm For Image Coding

With the development of astronautics science and technology, high-resolution space images are widely used to all fields of the national defense and space sciences. Raw-images acquired on each kind of scientific imaging instrument are very large volumes of data. Because the contradiction between the magnanimous data of high resolution sensor and the limitation of download-channel-bandwidth is more and more prominent, real-time, highly effective image compression algorithm to reduce the transmission band width has been the inevitable choice.In recent years, the still picture compression technology progresses very fast, lots of outstanding image compression algorithms are emerged, such as JPEG, EZW, SPIHT as well as JPEG2000 and so on. But these algorithms have their own deficiency in the space exploration domain and limit their application in this field. Therefore, the CCSDS organization officially proposed an algorithm with low complexity in view of the space image compression in November, 2005. This algorithm application locates in the high-speed equipments of the outer space flight vehicle. One can understand and apply it without the complex algorithm knowledge. It supports highspeed low power hardware realization; moreover, the compression performance of this algorithm is as good as SPIHT and JPEG2000. So it has the good application prospect in the outer space exploration.This paper focuses on the implementation of the CCSDS image data algorithm. the paper mainly contains the following parts:(1) The development of a Matlab program for CCSDS image data algorithm.(2) A Multi-bit-plane Parallel coding algorithm is proposed for CCSDS image coding algorithm, and simulationl results indicate that the performance of the improved algorithm is better than that of the original standard algorithm, and the complexity of the algorithm reduces obviously. (3) FPGA implementation in VHDL of the Multi-bit-plane Parallel coding are presented.(4) Performance of the proposed encoder is validated in FPGA hardware platform.