The Design And Realization Of Scheduling Control Module Of High Speed Image Collection System

The background of the topic is the testing of 3D motion parameters of test-engine nozzle and calibration of the dynamic in the rocket engine cold / heat testing, measuring and processing the marks In the process of the trial in real-time. In-depth understanding of the state of the domestic and international image processing technology applications and development, we adopt the design method of combination of embedded real-time image acquisition and processing based on DSP and FPGA.The center of the dissertation is hardware design and logic programming of the collecting-part of the system. We use FPGA chip typed EP1C6T144C8 of ALTERA. As the hardware platform for camera timing control, data transmission, the control of all modules in the board and system clock modules matching etc. We use TMS320C6416T new products of TI as image-processing processor. In addition to the selection of major chip in the hardware design, also including cameras and Embedded Systems Interface Design, DSP and FPGA communication interface design, FPGA power module design and FPGA JTAG program memory and interface design.In logic design, the FPGA chip is logic programmed, making it possess the function of camera timing control, data transmission, the control of all modules in the board and system clock modules matching etc. First, logical steps in the design and program of complete module are given. And base of the function, it is divided CA-D6 camera timing control module, data receiver module, and DSP communications module, remove burrs watchdog counter module etc. After analyzing input and output of each module, I achieved designing and programming of each module. All expected result is achieved after whole simulation, it validates the design and realization of scheduling control module of high speed image collection system to be valuable.