Research Of Estimating Leakage Power In Digital Integrated Circuits

As the rapid development of the IC technology, IC industry has entered the deep-submicron and nanoscale era. Power, especially leakage power, has become one of the VLSI designers' focuses as well as area and speed. In deep-submicron regime, the mechanisms forming leakage are more complicated. Leakage is becoming a significant contributor to power dissipation in CMOS circuits. Leakage optimization and leakage analysis are urgent to be adopted. Estimating leakage quickly and correctly is the foundation of leakage power optimization. Nowadays, method to estimate leakage has not been paid enough attention to. The purpose of this thesis is to estimate average leakage power of digital CMOS circuits quickly. A macromodeling method has been presented in this thesis to estimate average leakage power in RTL.This thesis consists of five chapters. Chapter one is the preface. In this chapter the background, target and advantage of this thesis is introduced. In chapter two, the components and mechanisms of leakage are discussed. The influences of the productive technology on leakage power have been analyzed by experiments. In chapter three, issues concerning leakage estimation in digital circuits are discussed. A macromodeling method is presented to estimate the average leakage power of digital circuits in RTL. In chapter four, the method proposed in chapter three is verified by experiments and the results are analyzed. Data fitting is used to improve the method in order to reduce estimating error. In chapter five, the main work of this thesis is summarized. Besides, it puts forward some problems to be investigated deeply in future.