Research And Implementation Of SDTA High Performance Memory Subsystem

The evolution of VLSI technology has made the gap between the performance of microprocessor and memory system much deeper. Memory performance has become the bottleneck of a processor now. At the same time, new applications are changing from compute-intensive to data-intensive. These data-intensive applications have the characteristics as follow: data-intensive, better spatial locality but worse temporal locality, requiring higher bandwidth of memory system. Those memory system in the past can't meet the need of these new applications.This thesis proposed a high performance memory subsystem based on the Synchronous Data Triggered Architecture(SDTA) which is designed for data-intensive applications. Primary innovative works of this thesis can be summarized as follows.Firstly, a hierarchy memory architecture was proposed. This memory architecture includes the Memory Flow Controller(MFC) in the Process Element and the External Memory Controller on the system bus. The MFC consists of DMA Engine, Memory Management Unit,Instruction Cache and Local Store.Secondly, aimed at reducing the complexity of designing and programming, a cache consistency model in SDTA processor was proposed.Thirdly, several optimizing technologies of memory accessing are proposed: the priority arbitration mechanism,accurate interruptions mechanism, virtual dma queue mechanism in DMA Enging and several technologies which can improve the address transforming process in MMU.Fourthly, this high performance memory subsystem was implemented based on the above studies. The verification and test of this memory subsystem were also fully exploited.The SDTA high performance memory subsystem based on the above studies can provide excellent data path and instruction path for clusters in SDTA processor. The performance test results prove that this memory subsystem can achieve relatively high bandwidth for many data-intensive applications.