Two-Stage Scan Architecture For Low Power Path Delay Fault Scan Testing

Along with fast development of very large scale integration (VLSI) circuits, the growing transistor density and the increasing operation frequency have made power dissipation an important issue in both design and test. Previous work has pointed out power dissipation in CMOS circuits is proportional to the amount of switching that takes place, and switching activity in an integrated circuit can be much greater during test than during normal operation, then test may generate more heat and damage the chip. Minimizing power dissipation is significant in improving the reliability of chip, and reduction of power dissipation permits the use of smaller package size, this can reduce weight of portable products and prolong battery life. On the other hand, reduction of power dissipation limits the number of modules that can be tested simultaneously or the speed at which the tests can be applied, this in turn impacts test time and test cost.In this paper, an improved two-stage scan architecture of path delay faults is proposed for low power scan testing. Scan flip-flops are grouped based on structural analysis, scan flip-flops in the same group share the same pseudo primary input in the test generation circuit; a signal hold unit is added to the first stage of the two-stage scan architecture, then two-stage architecture can be applied to path delay testing; scan flip-flops are divided into different clock domain, only a small number of them are activated when applying test vectors; a new scan apply method is proposed to reduce test time and test power, test vectors only scan in first stage, not scan in second stage any longer; a new XOR network architecture is proposed to compact test response, which avoid any aliasing faults. Experimental results demonstrate that using the improved two-stage scan architecture, not only test power reduced greatly, up to 99% mostly, but also test time and test data volume decreased evidently.