The Research And Chip Design Of EPA Control System

The research and chip design of EPA control system is introduced in this paper.Traditional Ethernet, which has good performance in bandwidth usage and compatibility, suffers from the feature of "uncertainty" due to the algorithm it takes to solve the issue of data transferring on network. Unfortunately real-time is the most important feature that industrial control system requires. The work group including the organizations of Zhejiang University, SUPCON etc took three years to research the modification of traditional Ethernet and finally raised the Ethernet-based real-time network communication solution for industrial control system. It is Ethernet for Plant Automation (EPA). EPA now has been one of international industrial standard in Common Profile Family 14 of IEC 61784-2.The chip of EPA protocol tries to implement all the common functions which will not change much in different applications. Based on such a chip, the manufacturers can focus their mind on the designs of application layer while no need to care about the implementation of network communication. This chip therefore will lower the cost for the manufacturers to adopt EPA protocol and correspondingly increases the popularity of the first international standard in the region of industrial control.Based on the standard design flow of digital ASIC, this paper introduces the contents including system design of EPA control chip, logic design for EPA chip's modules, modules verification, FPGA implementation verification and the result and analysis of EPA chip testing. The key points of this paper include: (a) basic logic design theory which is summed up from the practice of the project, (b) the consideration of chip's system design, (c) design and optimization for memory allocation in the transmission buffer of EPA chip, (d) the implementation of Address Resolution Protocol (ARP), (e) the analysis and the verification of the synchronization precise for Precise Time Protocol (PTP) and (f) verification and test for chip's FPGA implementation.EPA chip's FPGA implementation can works stably and all the designed functions work properly which verifies the correctness of logic design. In this test, test programs based on Visual Basic (VB) and network analysis tools such as Ethereal are used.The verified design of EPA protocol has been manufactured in the process of SMIC0.18um and QFP80 is used as the package. Most of the designed functions work correctly as shown in the FPGA implementation. Unfortunately, some logic error occurs when transferring the FPGA implementation into the ASIC implementation when the FIFO structure is designed. The crux of this problem is analyzed based on the logic design theory in this paper and several measures are proposed to avoid similar mistakes in the future.In this paper, we propose a novel technique for logic design which divides the flow of logic design into two parts: information presentation and information transferring. This technique, which comes from the practice and is proved by the practice, as we know, has not appeared in any teaching materials or journals. The second key innovation in this paper is raising the algorithm for page-based non-contiguous dynamic memory allocator. Compared to the existing contiguous memory allocator, our proposed algorithm has better performance in memory usage ratio. The third innovation is the design of Precise Time Protocol (PTP). We first analyze the factors that affect the precision of PTP under the special background of EPA protocol and then prove our inference by careful implementation and novel tuning. The experiment result shows that the precision of our PTP module is under 200ns and the mean of time synchronization is under 30ns.