Design And Realization For Embedded Face Recognization System Based On DSP/FPGA

With the maturity of the face recognition technique, the face recognition system has already been widely used in many fields. Its typical applications contain access management system, attendance management system, social security authentication system, internet banking authentication system, photos correlation system and intelligent monitoring system. In order to reduce the cost and increase the flexibility for the system, it is necessary to design and implement an embedded face recognition system which can run offline. This idea can surely further popularize the application of the face recognition system.This paper gives a complete scheme to design and implement an embedded system for the face recognition field. It takes the process of system design and realization as the clues to the writing sequence, organizes materials and describes the entire system in the way from top to down.In the phase of the overall design for the hardware platform, several kinds of frameworks are discussed first. From these comparisons, the DSP+FPGA framework is chosen for the system. This design combines DSP and FPGA. It controls the image data to enter into FPGA first, and then come to the DSP. The FPGA plays as the coprocessor for the DSP. It preprocesses the data, and then transfers them to the DSP. The use of FPGA brings with so many ways to system design and implementation. The developers can reduce the tasks of DSP by increasing the preprocessing tasks of FPGA step by step. From the point of the partition of the software and hardware, that is to increase the tasks for the hardware step by step to reduce the pressure for the software, and then achieve the aim of optimizing the system performance. Compared with the previous frameworks, it is obviously that this kind of framework is more flexible and will be more helpful to optimize the system performance.On this basis, the overall design for program controlling and data stream controlling are bring forth. This part focuses on partitioning tasks for the two cores of ADSP-BF561, building the software framework and controlling image data. The tasks for software part includes: initialize the whole system, capture images and convert them into the format that can be processed by the recognition algorithm, locate the human face and recognize it, start the Internet module or local storage module, start the audio alarm module and process the user interface events.The detailed design begins when the software and hardware frameworks are finished. The chapter 3rd, the chapter 4th and the chapter 5th discuss the process of system implementation in the sequence of hardware, driver and software, and this sequence is just the same as that of the system debugging.The implementation of the hardware platform involves three primary parts: first, build the DSP minimum system, and that is about the design of clocking, power, reset and memory; second, implement the internal logic for FPGA, and that is about the image relative logic and image irrelative logic; third, implement the image capturing part, that is about the initialization for the CMOS image sensor OV7640, and hardware implementing process of the images capturing part. The other assistant modules such as Internet module and audio module are only introduced briefly.The device driver phase comes after the design of the hardware platform finished. First of all, this part introduces three ways to program the two cores of ADSP-BF561, and select the way one application per core to finish all the following development for the drivers and the algorithms. Then, it describes the implementation of the DSP peripheral drivers which would maintain the minimum system running. Finally, it discusses the drivers for image sensor, the process of image capturing and the way to judge a new frame. The DSP peripheral drivers involved in this part will be introduced in the above process. They are initialization for PPI, initialization for the DMA channel of the PPI and the mechanism of Blackfin event processing. These drivers for the system can make the system capture the correct images real-time, and these images will be processed in the future.The detailed design of software is discussed according to the image processed sequence. This part focuses on the optimizing techniques for the algorithms, and the optimizations will be implemented through fully using the structure of the Blackfin core.First, to the feature of the inserting values algorithm, it brings forward the method to calculate the value of special position pixels in two steps. This method reduces the times to access the external memory, so it speeds up the algorithm.Second, to the feature of the BF561 processor, it brings forward the method to configure CACHE, and adjust the code sequence of the inserting value program to increase the CACHE hitting rate. In this way, it speeds up the algorithm. Third, rewrite the C program using the special video ALU supplied by Blackfin and the special video ASM instructions. This method converts the serial manipulation that average multi-operands into a parallel manipulation. So it reduces the executing time for the algorithm.Forth, rewrite the C program using the DSP special MAC unit and the special MAC instructions. This method compresses the multi-cycles MAC manipulation into one-cycle manipulation, so it reduces the executing time for the algorithm.Finally, adjust ASM code sequence generated by the assembler of VDSP++ using the 64-bits multi-issue instruction. This method permits a 32-bit image processing instruction and two 16-bits operands fetching instructions to be issued in parallel. So it reduces the executing time for the algorithm.The above optimizing methods improve the real-time performance of the system a lot. The performance of the optimized system satisfies the requirement of the market.The other keystone cared by the software part is the synchronization of the two cores. The system needs a mechanism to control CORE B reads the RAW LOCATION BUFB buffer after the CORE A writes something into it, and CORE A can not update the data before CORE B finishes reading. The system designs a lock using the TESTSET instruction supplied by Blackfin to implement mutex for the two cores, and it controls the two cores not to enter into the shared memory together. On this basis, it implements synchronization further more by adding a flag in front of the buffer, and it controls the accessing sequence to the shared memory.A serial of testing schemes is given at the end of the paper, and they test the correctness and the real-time performance of the system. Many advantages and disadvantages are summarized and then the plans for the future are given.The advantages including:The structure of the hardware framework is doable, and it is suitable for the real-time face recognition system.The structure of the hardware framework is flexible. It is convenience for debugging, and it also leaves space for the system updating.The performance of the optimized algorithm is high, and it can satisfy the real-time requirement. The disadvantages including:The location of face and eyes is slow, because of the use of the modules match method.The current system does not make full use of the DSP and FPGA resources, and especially the face recognition algorithm is not optimized deeply.