The IP Core Design Of MQ Arithmetic Coder

With the advancement of network and multimedia technology, information technology has great development. People look forward to more qualified multimedia information. But the transfer of information is limited by the bandwidth of transfer line. And the restore of information is limited by the capacity of memory. So JPEG standard is not able to afford the requirement of still image compression any more.JPEG2000 is a new image compression standard, developed under the auspices of IOS/IEC JTCI/SC29/WG1 in January,2001.Compared with JPEG standard, the JPEG2000 standard not only has better compression performance, but also has many excellent features.JPEG2000 provides quality scalability, resolution scalability, region of interest (ROI) coding, and supports both loss and lossless coding in the same framework.The bottleneck of the JPEG2000 system results from the throughput of the MQ arithmetic coder. Since the encoding procedures are inherently serial processes with high dependency, arithmetic coding is very difficult to be pipeline, and the throughput is low. We first analyze the software flow of MQ-coding algorithm in JPEG2000 standard, on the basis of predecessor's research, and we modified some operations to suit hardware implementation. Then we proposed the four stages pipeline architecture. The proposed architecture is fully pipeline, and all algorithms of MQ-coder are executed in one clock cycle, so throughput was increased. This architecture is described by Verilog HDL and the simulation result is correct. Experimental result shows the encoder can work up to 60MHz on Altera's EP1S25B672 and occupy 1620 logic elements. This architecture achieve high throughput while use less resources.In the final, the conclusion about the thesis and the future work are given.