The IP Core Physical Design And Optimization Of YHFT-DSP

With the development of the IC design technology and manufacturing process, along with the increasing demand of the market, the problem more and more design engineers face is how to complete the layout design in the given time. On the other hand, In the dual role of requirement guides and technology drives, the idea of integrating the system on a chip comes forth, named the SoC. The module which has the characteristics of less area, better performance, lower power consumption, and more excellent reliability will be valued great IP, and will be repeatedly used by the system.In despite of IC design or IP design of SoC, physical design is always a difficult and important problem, such as placement and routing. Due to the process size is shrinking, more and more problems will appear, for example, crosstalk, EM and so on. Physical design is the bridge between the top system planning and low-level model. So it will take up the most important status in the design flow. This thesis makes some representative study on a series of issues about physical design in the base of the IP core design about YHFT-Dx chips .D3 IP has been delivered to user. This thesis contains:1. As the key step of the physical design, floorplan will influence the effect of the placement and routing directly. This thesis aims at the characteristic configuration then describes the method of adjustment and arrangement about hard macros and the plan based on the standard cells region, besides, educes a good floorplan manner.2. IR drop and EM problems is becoming quite important, and power should supply every cell, power grid bestrew all over the core. So power supply will impact on the performance, power consumption, area prodigious. YHFT-Dx IP core analyze power grid in the worst condition, combine exact analysis about power ring and strap, and control the IR drop within 5% of the supply voltage, and resolve the EM problem. Thereby, enhance the reliability of the system.3. Reduce clock skew and clock delay is the significant target of clock network plan and clock routing. This thesis describe the clock tree design flow and optimization based on the balance buffer tree CTS. Finally, the result indicates the global clock skew of the clock is less than 5% of the clock cycle, accord with the design goal.4. The placement and routing based on the timing driven and congestion driven may decrease the delay, satisfy with the object, and it is also helpful for routability, sequentially to reduce iterative degree. With the timing and congestion driven by using the Astro, the timing result is good and the efficiency is also fine. By the analysis of the result, in the typical condition the clock frequency is 6ns, achieve the design aim.5. To validate IP core is important in the design flow, it affects with the delivery. This thesis passed the verification and provided various views for the SoC design.