Design, Implementation And Optimization Of Finite Field Multipliers

The finite field arithmetic, elliptic curve cryptography (ECC) and the finite field multiplier are investigated in this thesis. ECC is the one of the known public crypto arithmetic which provides the smallest key size and the best strength-per-bit The calculation speed over finite field greatly affects the performance of ECC implementation. This fact has inspired many researchers to find ways on performing fast computations over finite fields, especially over large finite fields of characteristic two.The central theme of the thesis is an investigation of finite field computations and their architectures, particularly the irreducible trinomials and pentanomials. All the multiplier architectures proposed in this thesis are bit-parallel finite field multipliers which canimprove the efficiency of cryptosystems significantly.New structures of bit-parallel multiplier based on SPB and its weakly dual basis (WDB) over finite field are presented. To the fields generated by trinomials and pentanomials, the proposed structures have the shortest critical path up to date with nearly the same space complexity. Furthermore, it is easy for a designer to implement the proposed multipliers into hardware for their regular structures.Furthermore, by implemented the proposal of new structure of finite field multiplier using verilog HDL, and analyzing in detail the performance of algorithms in finite field and the performance of the proposal using EDA soft Design Compiler, Power Compiler, we have drawn a conclusion that this proposal structures have the shortest critical path up to date with nearly the same space complexity. Furthermore, it is easy for a designer to implement the proposed multipliers into hardware for their regular structures. We also optimize the power consumption of the proposal structure.