The Design Of Digital Circuits In CMOS Charge-Pump Phase-Locked Loop

The charge-pump phase-locked loop (PLL) presented in this paper is amixed-signal circuit. It functions as a frequency synthesizer for providing on-chip clocksignals. The circuit is composed of a Phase-Frequency Detector (PFD), a Charge-Pump,a Loop Filter, a Voltage-Controlled Oscillator (VCO) and a high-speed frequencydivider (Prescaler).A high-speed PFD that meets the requirement specified by overall performance ofthe PLL is designed. The PFD has a fine phase-detection ability while consuming verylow power. Its operation speed is improved by making use of true single phase clock(TSPC) -based flip-flop. A high phase-detection resolution is desirable for a PFD. The'dead-zone' of phase-detection is eliminated by elongating delay of the reset circuitwhile maintaining an acceptable phase-detection range and capture speed. A prescalerwith a dividing ratio ranging from 4 to 15 is also designed in this paper. An enhancedTSPC flip-flop structure is employed in this prescaler design to improve its speed. Therace problem in dynamic circuit as well as signal integrity is discussed in detail, andsome modification is suggested. A design guideline for implementing a circuit of higherspeed is also proposed in this paper. In addition, a start-up circuit for VCO, adivide-by-2 module and a circuit for testing the programmable prescaler are designed.All above circuits are laid out. A simple introduction to the manufacturing processis performed, then factors being taken into consideration in floor planning and routingthe circuit are discussed. The lay-out of each module, the package form of the chip aswell as back-end simulation results are also given.The charge-pump phase-locked loop designed in this paper is fully-customized,and it is to be taped out with standard mixed signal 0.18μm provided by SMIC. Itspackage form is PQFP-64.