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Research On Construction Of Irregular Reapeat Accumulate Codes

Posted on:2007-01-30Degree:MasterType:Thesis
Country:ChinaCandidate:C M YuFull Text:PDF
GTID:2178360215970016Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
Irregular reapeat accumulate codes are subclasses of both irregular turbo codes and irregular low density parity check codes. They are candidates for future error correction codes of communication systems. IRA codes combine many of the favorable attributes of turbo codes and LDPC codes. Like turbo codes, the encoders of IRA codes are very simple and they can encod in linear time. Like LDPC codes, IRA codes can be decoded with low complexity iteration decoding algorithm. It is a significative task to construct IRA codes which have flexible parameters.Study some construction methods of LDPC codes. (1024,3,6) LDPC code with MacKay's method and EG(1023,781) code with finite geometriy method are constructed, and they are simulated with computer.RA codes and IRA codes are compared based on the analysis of their structure. The influence of degree 2 variable nodes to decoding performance is analyzed.How to design degree distribution of IRA codes on the binary erasure channel is studied. Degree distributions of IRA codes are derived from density evolution using Gaussion approximation based on the Gaussion approximation of regular and irregular LDPC codes. The parity check matrix is then derived. The design scheme of codes construction platform and the flow chart are provided. The design results are simulated with computer, and it results that the performance of IRA codes can compare LDPC codes of same length and rate. The performance is improved with the block lengths becoming biger.The encode rules of DVB-S2 standard and the structure of LDPC codes which the standard employed are anatomied in detail, then that the LDPC codes are a class of IRA codes is deduced. It can be kown from simulation results that IRA codes used in DVB-S2 have good performance. The encoder of length 16200 and rate 2/3 IRA codes is designed and implemented with FPGA, and the corresponding decoder structure is designed.
Keywords/Search Tags:Irregular Reapeat Accumulate Codes, LDPC Codes, construction, degree distribution, Guassion Approximation, DVB-S2
PDF Full Text Request
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