Design Of Deblocking Filter For AVS And H.264

The application of multimedia video compression technique grows very rapidly with the development of information technology and digital signal processing transmission. Both in familial amusement field and professional communications device field, or both in very low-cost consumer electronic product and very expensive specified device aspect, we can find that the compressed video technique plays an important role.The digital and high definition of audio-video products has become the trend of the consumer electronic.At present, the dominating new standards used for HDTV video compression are H.264 and AVS, both of them adopt block-based integer transform, quantization and block-based motion compensation, which will be the source of blocking artifacts and will reduce the subjective video quality and compression performance. So the adopt a filter to remove blocking artifacts.On the base of analysis the deblocking loop filter algorithm, this paper proposes an efficient architecture to realize the deblocking loop filter in H.264 and AVS. As a sub-module in multi-mode video decoder chip, our design supports the reuse of H.264 and AVS. And also adopts the parallel pipeline to improving the filter efficiency.In this paper, we use the Top-down design method in whole design. In order to verify decoding algorithms and provide test vectors for every module, we designed C model first, then do the simulation in every design step. We also analyze the circles of parsing process for H.264 and AVS video streams. At last, we do the FPGA verification and ASIC synthesis. The decoder can decode standard-definition video in FPGA and can decoder high-definition video in real time if use 0.18μm CMOS.