A Fast And Low Power Consuming DFT Design Method Based On Scan Array

To promise the quality of the integrated circuit products, the test is essential, however, the integrated circuits which will be tested being more and more complicated and integrated turn to making test be more and more difficult, test cost higher.To cut the test cost, it needs to bring into the design norms in order to test integrated circuits easily, through additional hardware or changing the circuit structure, make the designed electric circuits be easy to test, namely the Design for Testability (DFT).The consumption of the electric power directly decides the life span of the batteries in the integrated circuits;The development of the VDSM makes hundreds million transistors can be integrated on a single chip, and work with the frequency of several thousands trillion Hertzs, too high power consumption will restrict and influence the function of the system, even damage chip;The higher calories which the higher power consumption bring out make the chip encapsulation and coolant device's cost increase more, even there are technique restrictions.The power consumption under test mode of the integrated circuits would be higher than in normal work mode, analyze the power consumption source and try to lower the test power, can economize the test energy(particularly important for the locomotive equipments), can also lower the possibility of burning chip to bad because of test.For the sake of exalting test efficiency, we should also reduce test time.The essence of DFT is to make the electric circuits test easily, it also requests to decrease the test time basically.Considering the test power consumption and test time in the process of DFT is the content that this topic mainly studies.This topic puts forward a kind of DFT method which lowers test power consumption and decreases test time based on scan array: First expound and elaborate the scan array structure which puts forward in the literature, analyze and prove the usefulness of lowering consumed test power by theories;apply the concept of overlapping slice on scan array, for decreasing test vector which will be placed on, result in decreasing the test time;put forward a kind of piece partitioning method, make the transition number of adjacent different overlapping slice and total transition number of the test pattern less, lower the test power consumption further.To verify the accuracy and usefulness of the method which this thesis puts forward, do a series of experiments.From the experiments results, the method that this thesis puts forward comes to the result of the expectation.