Reliability Research And Verificaton Of Multi-IP-Reused SOC

SOC (System-On-Chip) is a new IC design technology in recent years. It bases on traditional IC design technology, but has a lot of differences. It changes IC design technology from "bottom-up" to "top-down". The elementary components of SOC design are function module and subsystem. This kind of chip contains one or more main function module, such as CPU core, DSP core and other specific application function module, and also some other function module, such as SRAM, ROM, EPROM, FLASH, DRAM and universal or specific I/O function module. All of these function modules are accomplished by standard IP.SOC transform the electronic design from PCB-based system design to chip-based system design. As the SOC design is more and more complex, the reliability is more and more important. Facing this reality, we have a deep research into reliability in SOC design, and use all-around reliable strategy in our design, make so-designed SOC achieve high reliability, and it can be used in high reliable application region. In this subject, the SOC we designed abides by AMBA (Advanced Microcontroller Bus Architecture) and conform to SPARC (Scalable Processor ARChitecture). Multi fault tolerance technologies have been used in our design, such as Parity check, TMR (Triple-Modular-Redundancy) register, on-chip EDAC (Error-Detection-And-Correction), Pipeline restart and force CACHE lost. Design logic has been analysed, research points have been introduced and VHDL code of main IP core has been given in the paper. Almost all CPUs have used some normal fault tolerance measures, such as parity check, pipeline restart. All pipelines copy before writing technology has been used in IBM S/390 G5. Multi ECC coding technology has been used in Intel Itanium. But none of these CPUs has the fault tolerance strategies as sufficient as this so-designed SOC. This SOC has a high reliability through our verification.Verification is a hard point in SOC design. There are a lot of IP cores integrated in SOC. these IP cores are not independent, but have data alternate and bus race. The real circumstance can only be simulated by co-verification of IP cores. As the scale of SOC is larger and larger, verification becomes more and more important. It has become a great challenge and a bottleneck problem in SOC design. There are many verification methods now, and they all have their own advantages and defects. In this subject, a SOC logic verification platform based on large capacity FPGA was built to verify so-designed SOC. The result shows that this platform runs reliably, and so-designed SOC has high reliability through this verification. At the same time, we have verified SOPC based on nios ii core on this platform. It shows that so-designed verification platform has a general use for SOC verification.This is a thesis for research and development, which serves for practical applications. Reliability is of first important for any application system. We have made a deep research into multi IP duplicated SOC and verify it. This kind of high reliable SOC has a great application value in high reliable application region, such as industrial control, medical control and aerospace especially. In more and more reliable applications, this kind of research has a great application foreground. At the same time, the verification platform we built can be used as a general verification platform for SOC design.