The Hardware Implementation Of The Information Retrieval Acceleration Based On The Embedded Chip Multiprocessor

Along with the amazing development of the computer and Internet technology, Information Retrieval (IR) has become a key technology almost in all aspects of our life. Accordingly, how to better the performance of the IR through improving the efficiency of hardware has been regarded as a significant research direction. In company with the progress of the integrate circuit technology, the chip multiprocessor, especially the heterogeneous chip multiprocessor which provides a perfect platform for the IR technology, has gradually become the mainstream of the computer development.The relatively traditional way, which adopts the parallel calculation arithmetic, usually accelerates the speed of IR by increasing the number of processor. Meanwhile, designing the ASIC accelerator to suit specific appliance and calculation arithmetic provides us with another alternative. However, these methods either fail to combine customized core and general core, or fail to apply to different ways of IR. Based on this, this thesis tries to explore the possibility of accelerating the speed of IR via the Heterogeneous Chip Multiprocessor technology.This thesis mainly focuses on the system of a single main core working with several synergistic processing elements (SPEs). The main core is a PowerPC 405 and the SPEs are specially customized for the calculation of IR. In order to achieve an accurate research result, the author has designed a 128-bit parallel core and a RISC instruction set with the several SIMD instructions inside, which can greatly enhance the efficiency of IR, when the key words sequence is less than 128 bits. If necessary, the SPEs can make use of the local storage (LS) to increase their calculation capacity. In addition to this, a special mode of data storage and a flexible organizing form has also been worked out.This thesis describes a program model of retrieving information by means of the user-defined instruction set. The thesis also gives the readers a detailed description of the whole process of IR, including the distribution of data, the organization of the LS, the system operation and the analysis of the calculation result. A design model under the circumstance of multi-assistant-core and multi-system is also offered as a further extensionThis thesis attempts to carry out and verify the Heterogeneous Chip Multi-processor technology system based on the Xilinx Virtex4 ML403 development platform. The research findings have been tested in different ways and compared with the general processor. According to the result of test, this system can enhance the performance of processor by 7 to 13 times without regard to the difference of calculation arithmetic. In conclusion, the system of Heterogeneous Multi-core technology is an efficient way to improve the speed and quality of IR.