Design And Research Of Hardware Accelerator On H.264 Encoder Based On ARM ESL Platform

As H.264 video compression technology is widely used nowadays and the researches on H.264 are more and more, one target is to achieve the high speed of compression on the basis of ensuring the encoding quality is not influenced.The ASIC design about H.264 decoder is successful in china and abroad, but in comparison, encoder is more complicated in algorithm and ASIC design so that the whole world is still researching on it.As for this project, the target is to find a reasonable path to divide the software and hardware by analyzing the timing cost of H.264 code. Finding out the section located at the bottom layer, much timing cost and calculating quantity, easy dividing between software and hardware, high parallel degree and low hardware spending, the architecture of software and hardware co-design will be realized on an ESL system simulation platform to check its function and performance, The result shows that the hardware module divided may save about 30% timing consumption by achieving the right compression without reducing the quality of the video. It's a reasonable hardware accelerating method for speeding up H.264 encoder.