Research And Design Of A Dual-band Low-noise Amplifier In 802.11 A/b/g Application

In recent years, the WLAN market shows a multi-standard co-existing situation. The wireless communication devices need to be compatible to all operation modes. The method of applying multi-transceivers for multi-bands became unsuitable as the cost is continuously going down due to the competition among manufactures. It is obvious that market needs multi-band transceivers. Mean while, the characteristic frequency of CMOS technology is becoming higher as transistor's size is scaling down, even more than 100 GHz. Being a low cost process, it will find more place in RF design. This thesis focuses on the multi-band low-noise amplifier, one of the critical parts of multi-band WLAN receivers, and implemented with RF CMOS technology.To low-noise amplifier, its performance is determined by the whole RF front-end. So the image-reject receiver is firstly introduced, and the receiver gain plan is specified. By linearity and noise theory of cascade system, the required performance for low-noise amplifier is derived out.Noise performance is the main performance of low-noise amplifier, so, the MOSFET need to be modeled before the design. The two-port noise model for MOSFET used in this thesis is based on the two-port network theory. The criteria of MOSFET noise-matching is also derived out from two-port network noise-matching method.The discussion of on-chip inductor follows noise analysis. As the most important passive component, a lot of works have been done on it. By comparing the advantages and the drawbacks of several modeling method, this thesis uses a novel substrate coupling model for on-chip inductor modeling. A comparison is performed between double-PI model and this model by simulation.On the foundation of above analysis, a multi-band low-noise amplifier is finally designed. The cascode topology is applied as the main structure of proposed low-noise amplifier for its good isolation character. The multi-band switching is carried out by multi input transistor and switch-able output network. A detailed design procedure is described.This design is implemented by HJTC RFCMOS 0.18μm process, and is tested on-chip.