| There are usually two methods to disign a MP3 player in an embeded system. First, we can totally rely on embedded CPU and DSP to realize the MP3 decoder through the program based on fix-point or float-point algorithm. Second, MP3 decoder can be implemented throuth pure hardware docoder. In the first situation, it depends on the high performance of CPU or DSP. If many tasks include MP3 decoder task is handled by CPU, higher performance is required. In the second situation, though specific hareware can get higher performance and lower power, it doesn't have the usual ability of process.In this paper, the research focuses on the implementation of a MP3 player for a SOC chip Garfield on an operating system ASIXOS which are designed by Asic Center. This research relies on the the project "16/32 bit RISC embedded controller Garfield design". Garfield is usually used by PDA and other divices, which supply many peripheral of mobile devices with users. Garfield uses ARM7TDMI as the CPU core. Garfield intragetes MMA(Multimedia Accelerator) module and AC97 module for sound multimedia handler.The MP3 player uses eventflag communication mode and program mode of ASIXOS to realize the function of MP3. This paper focuses on MP3 decoder performance analysis and optimization.The optimization is based on the on-chip-memory, which greatly enchanced the performance of the MP3 player.In the first chapter, the history of MPEG standard and MP3 are introduced, then the structure of MP3 player are illustrated. In the third chapter, the method of optimization based on ESRAM is researched and the data of experiment are given. In the fourth chapter, the OS ASIX is firstly introduced, then, the design of high level application base on ASIX program is illustrated.By now, Garfiled has been taped out and produced through MPW(Multi-Project Wafer),and the prototype MP3 player has been designed. Now the MP3 player can run fluently on the prototype, which satisfies the requirements of the project. |
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