Study On The Crosswise Multi-Gate SOI MOS And Its Application In Circuits

In VLSI design, in order to improve the cost performance of circuits, an efficient way is to save the chip area. Silicon-On-Insulator (SOI) technology has been widely used in the field of low power and high performance IC, which not only owning to its low power and high speed, but also profiting from its advantages in low junction-capacitance, latch-up immunity, hardiness of radiation and high temperature. In this paper, a new structure device of the Crosswise Multi-gate SOI MOS is introduced, which can implement one device providing many drive currents. It is applied to the synapse circuits of neuron and the matching circuits design, using one Crosswise Multi-gate SOI MOS device to replace many traditional SOI MOS devices, consequently saving the chip areas.Based on Fully-Depleted SOI technology, a quasi-three-dimensional Crosswise Multi-gate SOI MOS and traditional SOI MOS model of channel length 0.5 μm are establish by the employing of ISE TCAD. Compare the electronic-hole density, electronic-hole current density, electronic mobility and electronic velocity of the Crosswise Multi-gate SOI MOS with traditional SOI MOS under the same geometric and physical parameters. The comparison results show that there has a current passage in the Crosswise Multi-gate SOI MOS where only the gate is existed; the bare region between gates does not have current passage under the strong electric field influence; the drain-source region cover with gates is also not affected by the strong electric field. Next, the drain currents and the transfer characteristics of the Crosswise Multi-gate SOI MOS are simulated, and the comparison with the traditional SOI MOS is discussed. The simulation experiment results show that the drive currents of the Crosswise Multi-gate SOI MOS are proportion to the width of gates; the drain current is nearly identical when the channel width of traditional SOI MOS is the same as the gate width of the Crosswise Multi-gate SOI MOS; the threshold voltage is not changed with different gates working, and isthe same as the threshold voltage of traditional device.In addition, a top process flow of the Crosswise Multi-gate SOI MOS is improved and simulated by the FLOOPS tool of ISE TCAD. It satisfies the need of the Multi-gate structure via the structure and grid doping diagram. The Crosswise Multi-gate SOI MOS is applied to the Multi-jumping times and Multi- threshold of neuron synapse circuits design and the matching circuits design. The simulation results show that the circuits are not only correct and reach to the design index, but also effectively save the chip area.