Research On User Control And Administration Of Access Convergence Router

Controllability is the foundational requirement for network carrying out high-speeding, steady, safe and reliable end to end services under the condition of large scale subscribers. Ethernet technique is applied to broadband IP access network for its advantages of low cost, simple protocol, mature technique and easy-upgrading. User control and administration becomes the key factor of ethernet based broadband access network achieving the goal of telecom operation. This paper provides an analysis of user control and administration and presents some methods to solve key techniques of equipment developing based on network processor. The main contribution and originality as follows:A solution to user's access administration, IPTV service warrant and band control, IPTV channel switch is given in this paper.A hash-based low collision probability packet classification solution is presented in this paper. CRC-32 algorithm is adopted as hash function and an recursion algorithmic method is provide to calculate alterable length target code. CRC value can be calculated within only 8 instruction cycles for 128bit target code. CRC-32 algorithm has the good performance of randomicity and low collision probability. Hash collision chain node consolidation is proposed to quicken up chain search. This solution can be used in domain of multi-dimension packet classification easily.A modified DRR algorithm (pre-sorted low delay DRR) is proposed to schedule packet. This algorithm doesn't need read SRAM to get packet lengths while schedule a packet out. And two active lists make the scheduler serve active queues by turn and smooth the flow burst. Simulation shows that the Pre-sorted low delay DRR have the same fairness as DRR and lower queue average delay.A new flow traffic measurement algorithm based on two-layer memory hierarchy is given. Such memory hierarchy is constructed by small high-speed memory on the 1st layer and large low-speed memory on the 2nd layer. The two-layer memory hierarchy makes a better tradeoff between space and speed. The algorithm proposed in this paper has a smaller and fairer estimation error. To reduce SRAM read&write instruction and improve throughput, local memory of network processor (Intel IXP2800) is used as 1st layer memory and SRAM as 2nd layer in implementing.