Transient Analysis Of IR-drop For Power/Ground Network

With the advance of semiconductor manufacturing, EDA tools and VLSI design technologies, circuits with increasingly higher speed are being integrated at an increasingly higher density. This trend leads to a voltage drop on the Power/Ground network, commonly referred to as the IR-drop. This IR-drop will cause supply voltage variation, reduced noise margins, higher logic gate delays and slow overall circuits. In the worst case, it causes chip functional failure so that the evaluation for the power distribution is very important. But current commercial simulation tools are not able to deal with this kind of huge power grid system. It has been become an attractive topic in the advanced IC design field.A modified random walk algorithm is presented based on the traditional random walk algorithm and the characteristics of the conductance matrix of P/G network in this thesis, which can be used in VLSI P/G network transient analysis. Firstly, the whole P/G network is separated into three parts: the solved region, the active region and the faraway region. With this strategy, the program is recursively implemented till the final results of the whole network are obtained. Secondly, a speed-up approach is applied in the transient analysis. Random walk is only needed at the first timestep while in other timesteps the walk records are just used to compute the voltages. Experimental results show that this algorithm has desirable accuracy, and is much faster than the existing methods such as the traditional random walk, CG and ICCG.