VHDL Realization Of Block Cipher Algorithm Rijndael

Rijndael algorithm is maximum level representative in block cipher at present and the hardware implement of Rijndael algorithm will substitute for DES hardware encryption chip in the future several dozens years to Become a tendency. Therefore studies and designs for Rijndael algorithm FPGA implementation have the important theory significance and the realistic value.On the basis of the analysis of Rijndael algorithm, this article first improve each transition function operation order of decrypt round transformation, that encryption and decryption process round transformations are the same sequence. Also carries on the optimization to the mixcolumn transformation and inverse mixcolumn transformation by Galois field, linear algebra and matrix theory, and the equivalent round transformation expression of the encryption/decryption algorithm is proposed, so that the resources of FPGA can be shared completely and simplified the operation of round transformation greatly. Based on the Full Pipelining Architecture, integer circuit structure as well as round transformation, key expansion and each sub-module electric circuit structure are designed by EDA method, and then each part is depicted with VHDL.By using integrated environment Max+plusII10.2, simulation test is done and the algorithm is realized which encrypts data and decrypts data with 128bit cipher keys. Based on APEX10K series EPF10K200SBC356 chip of Altera Corporation, with 25.5MHz operating frequency, the encryption speed is 2,720 Mbit/s, the decryption speed is 1,813 Mbit/s. The simulation results indicate the correctness of the circuit design and achieved the Gbps rank design goal of the encryption/ decryption speed.