The Research On The Coding Method Of SOC Test Pattern Compression

With the IC design rapidly transform to the SOC (System-on-a-chip) way, they integrate the preverified and predesigned core into one chip. This way cut the TTM short, but also takes challenge to testing. The increasing test patterns and the increasing test time leads to the higher cost. For resolving this problem, we should compress the test patterns. This paper is based on some classic test pattern compression methods, and also summarizes the advantages and disadvantages of every method. And we make some improvement based on it. The main work of the dissertation is as below:1. Summarize different encoding technology, and also analyses the specialty of different methods. The analyses are emphasize on the alternation and run-length code and the fold counter, find out where can these methods apply, and also find out the disadvantages of the two methods, and make improvements in the later work.2. It's a classic method to encode the constant Os in the differentiate vectors, but this way can not accommodate the 1s and the 10s, and the alter and run-length code can accommodate it. We precompute the test patterns to make it to be encoded more easily by alternation and run-length codes. The result shows that the effect is obvious after precomputating.3. Aiming at reseeding issue in the classic fold counter technology, this paper presents a method, it doesn't need reseeding. After generate all the patterns of the fold set, it can transform through some interim fold set to the next fold set. This paper will prove in mathematic way that there exist the interim fold set and the number of the fold sets that should be transformed through is the least. This method needn't heavy hardware cost, and the communication protocol is simple, and the compression is obviously. This method can handle isolate point by classic fold counter technolog and also expand the usage of the fold counter technology.