The Module Design Of Video Decoder For The Standard Of H.264

With the recent development in the field of multimedia, computer, network,HDTV and communication, the techniques of the digital video compression have beenwidely studied and become a hotspot of the research in the field of the informationtechnology. During several years, many international standards about imagecompression have been set up by ISO and ITU,such as JPEG, H.26x, MPEG1/2/4 etc,which provide the same interface for different applications and then make the furtherdevelopment of the technique on Video processing.Real-time video data processing has very high computing complexity. The newprogress in VLSI technology makes it possible to realize these sophisticated imagecoding algorithms which require high computional power, and accelerate theexploitation and production of video compression chips with a high speed, highperformace and low price. In some case, the key of video compression technology isthe realization of video compression arithmetic in VLSI field. So it is very promisingto research the standard of compressed coding based on advanced hardware system.The emerging H.264/AVC video coding standard was developed collaborativelyby the ITU-T and ISO/IEC. By adopting a number of new coding techniques,H.264/AVC has achieved a significant improvement in compression performance anda "network-friendly"viedo representation relative to existing standards.The purpose of this dissertation is to do some research work on the VLSIarchitecture of H.264 decorder. First the author describe the systematic approach todesign the inverse integer transform and quantization in H.264/AVC because of it is anew standard. Unlike the popular 8×8 IDCT used in previous standards, thesuperiority of integer transform is considerablely obvious. Then IQ arithmetic and thestructure of VLD coding table was discussed. Finally, the hardware structure of thesemodules was given in the last chapter, and the hardware test was done on thehardware development platform.