Implementation And Optimization Of H.264 CODEC Software Based On TMS320DM642

The H.264/MPEG-4 AVC video compression standard has achieved a significant improvement overall previous video compression standards. In terms of coding efficiency, the new standard can provideat least 2x compression improvement over the best previous standards and substantial perceptualquality improvements over both MPEG-2 and MPEG-4.But the H.264 standard is significantly morecomplex than any of the previous standards. Consequently, the H.264 CODEC is expected to besignificantly more demanding in terms of computations and memory requirements. Since any decodershould be able to handle all "legal" bit streams (i.e., worst-case scenario), making the decoderimplementation even more complicated. Moreover, the development of an embedded CODECimplementation where the internal memory size is limited is a challenging task.The TMS320DM642 Digital Media Processor (DM642) is the highest-performance fixed-pointDSP from Texas Instruments. The DSP core processor has 64 general purpose 32-bit registers andeight highly independent functional units -two multipliers and six arithmetic logic units (ALUs) withVelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include newinstructions to accelerate the performance in video and imaging applications and extend theparallelism of the VelociTI architecture. The DM642 uses a two-level cache-based architecture andhas a powerful and diverse set of peripherals.The main task of this thesis is to develop and optimize H.264 "baseline" CODEC software on theTexas Instruments' TMS320DM642 Digital Media Processor. With its 600Mhz processing power inproduction today and an aggressive process technology roadmap for continued higher clock rates, thisDSP is most suited to overcome the complexity and computational requirements of H.264. By carefulexploiting the algorithm and instruction-level parallelism inherent in the H.264 CODEC;thecapabilities of the processor, such as its powerful instruction set and versatile EDMA controller;andsuch tool chain capabilities as code sectioning and code overlay, we can meet the challenges of highcomputational complexity with a low-complexity solution.Our H.264 decoder is optimized to provide 100-120 fps decoding performance for QCIF resolutionvideo;or 20-30 fps decoding performance for CIF resolution video now. Our H.264 encoder isoptimized to provide 15-25 fps encoding performance for QCIF resolution video.