VLSI Implementation Research In Digital Image Parallel Processing

How to increase processing speed has been one of the key problems in digital image processing, which has been studied by many ways and still been difficult to be broken through. Image parallel processing technology has proved to be one of the most effectual technology for increasing image processing speed. The appearance of EDA technology and the development of VLSI have provided a new design platform and amplitude's development space, so that it is possible to more fast and economically develop the high performance image parallel processing hardware.The Image parallel processing technology of chip design level are firstly analyzed in this paper, such as neighbor domain image processing algorithm and its parallel data structure, neighbor domain image parallel processor etc. Then three practical application cases of VLSI implementation design, which are Sobel image edge detector, Laplacian image edge detector and integer wavelet transform, are mainly discussed through the combination of algorithm's introduction, the system's overall design, the design means of main models and the analysis of simulation .In the VLSI implementation design of Sobel image edge detector, the buffering of input data and data processing are realized by FIFO stack, the updating of vertical pixels are realized by serial-in and parallel-out modules. Repetitive data input are avoided and pixels_processing_window data's updating are realized by shift-register circuit. The system processing speed is increased by designing parallel and pipelining filters and repetitively using four filters. Thus the pipelining input of neighbor domain processing data and the parallel processing of varies kinds of level and whole procedure data are realized, good real-time capability is also achieved. If the system working clock is 50 MHz, the detector only needs 0.105s to dispose a image with 1024*1024 pixels. Compared with single DSP(40MHz oscillator) and MCU(12MHz oscillator) application system, the system speed is enhanced by 10 and 400 times for each.In the VLSI implementation design of Laplacian image edge detector, High repetition read of convolution processing data are avoided and overall stream input of convolution processing data are realized through using shift-register to storage pixels and register to deal with serial-in andparallel-out procedure. At the same time, the system is optimized in efficiency and hardware resources by means of using distributed arithmetic with the highest speed to complete the convolution arithmetic.A stream-like processing result could come out from each clock period, it has good real-time function. If the system working clock is 100 MHz, the detector only needs 0.01s to handle a image with 1024*1024 pixels.Integer wavelet transform, a kind of algorithm based on lifting scheme, which has the advantages of fast computing speed, storage economization, can be freely used to dispose any size of image and realize lossy and lossless compression of image. In the VLSI implementation design of Integer wavelet transform ,the design difficulty is decreased by the means of top-down design. Data buffering, parallel processing and piping processing are realized by varies kinds of data registering or latching. Data's multiplication, division and its rounding computation are realized by shift-calculation .Complex sequential control of wavelet transform is realized by multilevel state machine. Wavelet multilevel transform is realized by designing common decomposition and synthesizing modules and parameter access modules.