Research On Implementation And Optimization Of BWDSP100 Compiler

Most of the modern DSP processors are based on VLIW architecture,it gets high-performance processing ability through mining instruction level parallelism(ILP) by the compiler, namely issue more instructions in the same cycle. As the number of instructions issued in the same cycle increased, more and more resources are needed. Thus using centralized register file has reached the bottleneck, so some DSP processors are becoming to use clustered register file, this is also a big challenge to the designing of compiler.The mainly work of this dissertation is developing C compiler for a DSP processor BWDSP100 produced by a research institute base on IMPACT, which is a retargetable compiler. And also, we did some research on compiler optimizing toward the features of DSP's architecture and application area. This dissertation has been divided to two parts, development and optimization. The work and contributions include the following three.Firstly, write machine description for BWDSP100. The machine description transmits the information of instruction set to compiler by describing the operation format, resource using, operation latency and operation of target platform. Thus, the back-end of compiler can be independent with target machine to a great degree and easily ported to other platform. We use MD language to write the machine description, which cut back our workload.Secondly, design clustering algorithm for BWDSP100. The main task of operation partitioning is to bind every operand of operation to a cluster. The algorithm should consider the dependence of operation to prevent that operands of an operation are bind to different cluster. We present a heuristic method based on Dataflow Graph(DFG), and optimize it with the considering of architecture, our algorithm got a 8% improvement over traditional algorithm.Lastly, optimize the compiler based on the architecture. We designed intrinsic function for BWDSP100 to use some special instruction in C language, and optimized for debug mode and FFT algorithm. Experiment results shows that the cycle of assembly generated by BWDSP100 compiler gets 30% improvement over the DSP processor TS201, and even better when doing complicated calculation.