Physical Design And Solutions Of Some Key Issues For A Speech Processing Chip

With the continuous development of integrated circuit technology, the feature size of the manufacture process is narrowing down, while the size of design is getting increased, which brings a lot of challenges and puzzles to the IC designers, such as how to design a chip with better performance, lower power consumption, smaller size and higher reliability, and how to solve the problems due to smaller feature size of the manufacture process and bigger wafer, etc.The details and several key issues in physical implementation were discussed basing on the backend design of a speech processing chip. The key functional part of the chip includes a kernel decoding module and three peripheral functional units. Two ROMs, two single-port SRAMs and two dual-port SRAMs are also embedded in the chip. The backend process included data preparation, floorplan, powerplan, placement, clock tree synthesis and routing, and the flat flow was adopted in the design.Many details were considered in each phase of the backend implementation. Die size, various I/O cells and their positions were determined, and the macro cells were also placed. In the powerplan phase, power, ground and their connection were defined, then power rings and strips were designed. Timing, noise, routing congestion and some other factors were considered during the entire placement. Several optimization methods were carried out after the c lock tree synthesis. Many methods to prevent and repair antenna effect and crosstalk were also implemented during the entire routing process.