Research And Design Of Critical Technology For Multi-Core Architecture Targeting The Application Of Spmd

The technology of multimedia and wireless communication has gained rapid development these years. Many popular algorithms in these fields have a natural way to achieve parallelism, and they are very situable to be implemented on multi-core architecture. It becomes a key issue of how to design multi-core architecture without a significant increase of the complexity so that it can be more efficient on processing data in parallel way.In order to improve the performance of multi-core processors and simplify their structures, this design focus the research on the way of data exchange among each processing core of the multi-core processor and the mapping and implementation of the special parallel algorithms. This thesis represents a multi-core processor architecture targeting on the commonly used application of video processing parallel algorithms. The design uses the configurable shared register file and multi-layer-bus between the processing cores and the memory to create the data path among processing cores, in order to improve performance of data parallel processing and efficiency of data exchange. The proposed architer significantly reduces the implentmenting cycles for a range of algorithms compared to the traditional multi-core processors with shared cache.This thesis describes the individual processing core constructing the multi-core processor, the structure of the multi-core processor, the data exchange mechanism, the mapping and implementation of some common used video parallel algorithms and performance and evaluations of the multi-core processor and the algorithms.