Design And Implementation Of Mpsoc Platform Based On M5

In order to match the constraints imposed by the embedded system market in terms of performance and power consumption and keep on exploiting the high level of integration provided by the semiconductor technology, Multiprocessor System-on-Chips (MPSoC) have been proposed as a promising solution. However, as more processing elements are integrated, the HW architecture and SW design of MPSoC are becoming more complicated, and the design parameters need to be validated repeatedly. In this context, a fast and accurate MPSoC simulation platform is necessary to efficiently explore design space and co-design between hardware and software at the early development stages.According to the prevalent methodology of MPSoC platform, a fast and accurate full-system simulation platform based on M5 simulator is built for HW/SW co-design and design space exploration. The design of this platform is divided into two parts: HW modeling and SW porting. The HW modeling employs a novel SystemC-master multi-level co-simulation scheme to combine instruction set simulator and transaction-level SystemC simulator, which improves simuation precision with no expense on simulation speed. To support applications with different communication characteristic, two different implementations of network interface and its HAL are proposed. The designers will make the choice with the application characteristic to achieve higher performance. The SW porting includes configuring Linux 2.4 kernel of ARCA processor, customing file system and loading file system with RAM Disk. A novel interaction method between OS and MPI is proposed to eliminate the cost of data copy in communication process. With the mothod, the communication latency is reduced by 64%.In order to validate the MPSoC platform, a parallel MUSIC algorithm is executed on a four-core plaform, and the speedup obtained against sequential algorithm is 3.2. In order to analyze the bottleneck of communication process, the inter-task communcation process is divided into three parts, and the linear fitting communication latency formula of each part has been proposed which has been used in task mapping and scheduling algorithm for MPSoC.