Low Power Back-End Research For A Speech SoC Chip

With the advances in the process and the decrease of the transistor feature sizes, IC design has now entered the deep submicron and nanometer SoC design era. And the single-chip SoC is now achieving the development towards a larger area, higher frequency, and more complex direction. SoC design has faced of unprecedented challenges during the development. The most prominent issue is the power consumption. The seriousness of the power problem not only constrains the further improvement of the chip performance, but also makes the physical design of the chip become increasingly difficult. The problem is mainly reflected in the following two aspects: one is that the interconnect delay becomes the main factors of the chip with the decrease of the feature size; the other one is that the impact of leakage power consumption in the circuit is more and more critical. Therefore, understanding the power components, doing power estimation analysis, and being familiar with how to do low-power design has become the main problems that the front-end and back-end IC designers have both to concern.The low-power design methods are throughout the SoC design process. This paper studied low-power SoC chip design methodology, and the methods were applied to the back-end process of a speech SoC chip. Being implemented in the logic synthesis and route tools, the power of the chip was greatly reduced.The composition of IC power consumption and the low-power design methods in the different design levels were discussed first. And the details of the RTL and gate-level power estimation methods which was the fundamental of the low-power design application were studied next. Then a detailed research of the low-power design methods in the logic synthesis flow and the physical layout design flow was made on the chip.In terms of logic synthesis flow, starting from the technology library mapping theory, the low-power design methods of clock gating, operand isolation and different memory block access were mainly studied, and the theory and application about the low-power DFT was also presented. In terms of physical layout design, following by physical design flow, the low-power design methods was focused on successively in design plan stage, power plan stage, and clock tree synthesis stage. And the multiple supply voltage application in the SoC chip was also analyzed.