The Research And Implementation Of CDMA2000 Downlink Physical Key Technology

Recently, with the rapid development of communication technology, mobile communication has become an integral part of the People's Daily life, and plays an important role. With the unceasing development of internet technology and the increasing need of high-speed mobile data business, the voice services and low speed data business can not meet the need of most people. Therefore, the third generation mobile communication (3G) has been fully put into use, which is characterized by high data rate and multimedia service. CDMA (Code Division Multiple Access) technology, due to its good high security, low power and antinoise performance, has become the main 3G technologies. As one of the 3G mainstream standard, CDMA2000 has been widely used in the global. Its evolution standard EVDO can provide peak rate as high as 2.4 Mbps high-speed data transmission service. In the field of electronic design, FPGA as a new Programmable Logic Device (PLD), due to its high level of integration, high performance and high reliability etc, has gradually becomed a preferred method for digital hardware circuit design, which provides a hardware platform for this design.Based on thorough understanding CDMA2000 system principle, characteristics and protocol standards, this thesis detailed research on CDMA2000 downlink channel structure and characteristics, then design and implementation the pilot channel, sync channel and paging channel based on FPGA.First, CDMA2000 baseband processing hardware platform was designed and developed which based on Xinilx programmable logic devices FPGA chip, and detailed introduction was gived for each child module design. Then the thesis was completed the hardware platform debugging, including welding circuit components and chips, and using the instrument equipment and program to test each hardware modules, which can verify hardware work normally.Second, based on FPGA design ideas, and using hardware description language-Verilog, the paper modeling and design CDMA2000 downlink signal processing in each module, including the CRC check module, convolution code modules, interleave code module, pseudo-random code generation module and baseband forming filter modules. Those parts were analyzed in theory and designed in Verilog language, then given the simulations using the Modelsim and Xilinx developed software-ISE, finally, completed the FPGA realizing of each module, verified relevant protocol standards.In the end, based on the baseband processing hardware platform, the paper realized the pilot channel, sync channel and paging channel. And combining with the laboratory test environment, the paper verified the three channels and those sending channel messages, separately carried on the physical layer and layer 3. The verification results showed that the design was correct.The design has made some staged achievement, and has strong expansibility. The achievements of the designs which provide a solid foundation of the work in the future have practical values.