Research On High-Performance Cycle Accurate Simulation Technology For C67X Digital Signal Processor Instruction Set

Currently, DSP as a solution to the high-performance processor-intensive computing is increasingly being applied to many fields of embedded systems. With technological development, DSP hardware architecture, instruction set and pipeline becomes more and more complex, which brings simulation lots of difficulties. This paper focuses on the simulation of TMS320C67X's pipeline and the improvement of simulation performance.The paper firstly introduces the characteristics of VLIW architecture, and then analyzes the defects of pipeline sequence simulation model in delay slots, pipeline stalls and so on. So we use pipeline reverse order simulation model for instruction set simulation. The model firstly simulates the function of instruction execution stages, and the function simulation of instruction fetch stages will be happened at last. We will also presentation the reason and the benefits of the model. Furthermore, the paper analyses the performance bottlenecks that may exist in implementation of the model. Based on the analysis, we design two mechanisms to optimize the performance of pipeline model. According to the hardware feature, we design and implement the instruction simulation module, memory module, register module and files load module, together with the optimization module composed of entire platform.At last we use Whetstone benchmark, Dhrystone benchmark and Chebyshev low-pass digital filter algorithm as test suite. The result shows that not only the platform can simulate the instruction set correctly, but also has high performance. It is an experimental platform which particularly suitable to verify application and to expand custom features.