Implementation And Optimization Of H.264 Encoder On TILE64

With the development of multimedia technology and the wide use of video technology,the demand on real-time video-communications and high-image-resolution has become much greater. As a new generation of video coding standards, H.264/AVC can provide a high-resolution video coding efficiency, yet with great complexity. It is difficult for a single-core embedded platform to implement a H.264/AVC encoder, which can overcome the conflict between the high complexity and the real-time demand. However, the multi-core embedded platform may be one of feasible solutions,due to its stronger processing ability. Now it has become a hot research field in the study of video coding based on multi-core platform.This thesis focus on the implementation and optimization of H.264/AVC video coding based on TILE64 multi-core processing platform. Firstly, a brief survey of the function and hardware structure in the TILE64 platform are given in Chapter I. Secondly, the methods and steps of realization and optimization for H.264/AVC encoder based on TILE64 are introduced. To be specific, the first step is the instructions-optimization on a tile, and then, executing optimization by parallel-design on more tiles. For instructions-optimization part, from the experiment result of H.264/AVC video encoding, it can be concluded that the distortion-calculation, the integer transform and the interpolation module are the most time-consuming hotspots. Therefore a large number of instructions in the TILE64 Instruction Set,such as SIMD, are used in our system to achieve the purpose of lessening operations and reducing complexity. For parallel-optimization part, by the module analysis about the computation and independence, the reasonable idea of parallel-optimization is given. The practice is to let the filtering module run on one tile, and at same time, others modules be executed on another tile. The reason is that the filtering module is a time-consuming and relatively independent part. Finally, two possible parallel-optimization improvements are advised.The experimental results show that the instructions-optimization on a single tile reduces the distortion-calculation module and the integer transform executing time by 10% and 15% at most, respectively. And the execution speed is increased 3.5~4.5 times. On the basis of the instructions-optimization, the system performance is further improved through the above-mentioned parallel-optimization methods on the multi-cores. The speedup of 1.04 to 1.15 is obtained and the frame rate is improved 5.18 times at most.