The Hardware Design And Verification Of Intra Prediction Of AVS Decoding Algorithm

AVS (Audio Video coding Standard) is developed by China with intellectual property rights, which becomes national standard in the field of audio and video of China formally in 2006. There are many advantages with AVS standard like high efficiency of coding, low complexity of implementation, low license fees of patent and so on. With a widely used of multimedia, while promoting by China government, AVS standard has broad market prospects and broad space for development.Currently, in the field of embedded, there are three main design schemes with implementation of video hardware decoder in international. The first scheme is to design a ASIC chip, with a fast speed of decoding, but it takes a long time to develop and cost is high; The second scheme is to use a DSP processor to decode video. This kind of video decoder has high flexibility, and can be update. But it needs a DSP with high performance; The third scheme is to design a chip with the form of SoC. Inside of this kind of chip, there is a embedded MCU and hardware accelerator module. To compare with the second scheme, this scheme also has high flexibility and can be update, while needs less cost. So it is a better design scheme.This thesis emphasis on research of intra predication decode algorithm and implementation in hardware of AVS video decoder. Using the scheme of SoC based on FPGA, design a module of intra prediction algorithm of AVS decoder with the form of IP. We present the status and the development of technology for decoding of audio and video standard, introduce the origin and the content of research in this thesis in chapter one; We present some key technology for video decoding in AVS standard with a more detail method in chapter two; We present how to design a IP for intra prediction algorithm of AVS standard in chapter three; We present how to design a verification platform for AVS decoder under the scheme of SoC based on FPGA, and how to design an interface for Avalon bus in chapter four; In the end, We verify the IP module and get some conclusions in chapter five.