PRML Read Channel For High Density Optical Recording System: Research And Implementation

The technology, called partial response maximum likelihood or PRML, is originally used in communication for outer space. It was applied in Viking spacecraft for data transfer from the Mars to the Earth. In recent decade, PRML has been used in high speed optical record systems. Instead of trying to distinguish individual peaks to find flux reversals, a controller using PRML employs sophisticated digital signal sampling, processing and detection algorithms to manipulate the analog data stream coming from the disk (the "partial response" component) and then determine the most likely sequence of bits this represents ("maximum likelihood").As data density increases, the flux reversals are packed more tightly and the signal becomes much more difficult to analyze, because the peaks get very close together and start to interfere with each other. This can potentially cause bits to be misread from the disk. Since this is something that must be avoided, in practical terms what happens instead is that the maximum areal density on the disk is limited to ensure that interference does not occur. To combat this problem a new method was developed that takes a different approach to solving the data interpretation problem. PRML changes entirely the way that the signal is read and decoded from the optical disk.This paper emphasizes particularly on the research of PRML detection's implementation technology. After introduce the theory of partial response and maximum likelihood sequence detection, the way of using ASIC to implement PRML is expounded in emphasis. The modules of equalizer, timing recovery and Viterbi detector are implemented. At last, the application of PRML detector in DVD servo IC is introduced.We develop Viterbi decoder for supply higher data rate. First,the Viterbi decoder processes two samples at once, instead of just one by modification of the state transition diagram. It also can process more samples at once by the same way; Secondly, we also give a new method to avoid the increasing of area that caused by modification for supply higher data rate. It decreases the number of state by state sharing.All the program in this paper is programmed by Verilog HDL, simulated by Modelsim 5.6d, synthesized by Synopsys v2000.05.