The Design And Study Of Level Two Cache Controller On High Performance DSP Chip

DSP is a kind of CPU with specially designed structure, which is applied widely in many fields, such as communication, military, controller and household appliances.This thesis focuses on the architecture of the advanced mainstream DSP, especially the VLIW architecture. And the characteristics of the Cache controller on chip have been analysed in details. In our self-determined design of YHFT_D1, the Second Level Cache Controller (L2), which is programmable, has been adopted. We have applied the stand cell-based methodology in our research, finished the function design, the compatability design, logical synthesis and optimization. We have also proposed the idea of performance improvement.In the design, we have devided the Tag bank and Data bank into two levels. Only when LI accesses L2, and the Tag hits, can the L2 Data bank be accessed, which can reduce many waste accesses and reduce the power dissipation. Replace algorithm is pseudo LRU, and we have resolved the replace equality at the one or two or three or four way set associative. The signs of Tag are made up of Valid bits and Dirty bits and LRU bits, which are realized by registers, while the Tag is realized by SRAM. So, this is a good idea to reduce the power dissipation.By using the Design Compiler, at the worst case operation condition of 0.18 u technology artisan standard cells library, L2 has satisfied the requirements of both timing and area. Its frequency of the post-logic synthesis is 200 MHz and its area is 600 thousands square m.The analysis performance test of L2 has been done, its representative invalidation is 9.08%, and its shortest latency is five clock periods. The result of the test indicates that L2 satisfies requirements of the compatibility design.