The Design And Verification Of Embedded DSP Processors

The development of information society depends on the progress of information technology and signal processing technology. Many application systems such as mobile phones, digital TV sets and industrial equipments need high performance programmable digital signal processors (DSPs). Compared with application specified integrate circuits (ASICs), DSPs are more flexible to practical applications with the programmability. To meet with the requirement of high-end digital systems, high performance DSPs with the operation capability of more than several Giga multiply-accumulates per second (MACS) are required.Aiming to the great demands for high performance DSPs, a DSPs research project supported by national "863 projects" was carried out in the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS). As a part of this project, we designed a DSPs named DSP which is a 16-bit fixed-point DSPs. This thesis mainly discusses the design and verification of this uDSP.First of all, general principle of processors was described at three basilic aspects: instruction system, pipeline, memory system, and then we designed the architecture of the DSPs. Its main characteristics include: improved Harvard bus structure, six-stage pipeline, special instruction system and flexible addressing mode, etc.Then we designed the uDSP at Register Transfer Level (RTL) based on the design of architecture and according to the requirements of embedded DSPs. The embedded design is characterized by the reusable RTL code, not adopting full custom design to improve performance and excluding various peripheries and interfaces, etc.Design-for-Testabiliry (DFT) was also considered. At the early phase of design, the test requirements should be sufficiently taken into account; this can decrease the complexity of test- vectors generation, enhance the test coverage and reduce costs of test. So, the JTAG Boundary-Scan structure and RAM Built-in Self-Test (BIST) logic have been added into the core of uDSP to enhance the testability of the chip.Finally, the strict functional verification and timing verification was done. On the functional verification, we adopted the strategy of combining simulation with formal verification; on the timing verification, the static timing analysis method was applied. The synthesis of various verification methods brought the verification tasks to success and established the firm basis for the success of tapeout.