Research And Design Of Pipeline Magnetic Flux Leakage Inspection Control System On FPGA

In order to enhance the measure precision and expand the using area of the existing oil pipeline MFL(Magnetic Flux Leakage) detecting system to natural gas pipeline testing, detailed information of flux obtained by decreasing sampling time and space interval is needed. The huge amount of data produced by this will exceed the processing ability. So existing systems must be improved.FPGA(Field-Programmable Gate Array) is super large-scale, ultrafast programmable logic device that use extensively in recent years, Because it has merit of high integrated level( the single chip of system gate number integrated reaches up to ten million gates), the high speed( 200 MHzs and more than), programmable in system etc, has brought the breakthrough change for the digital system design, greatly drived the single chip and automation of the digital system design, has shortenned single digital system design cycle, improved design flexibility and dependability. In the ultrafast signal progress and in measure and control in real time has very extensive application.We regard FPGA as control's core of new-type pipeline magnetic flux leakage detecting system, research and design control's core of pipeline magnetic flux leakage detecting system based on FPGA. Design divided into three units : multi channel sampling control unit, data processing unit and data store control unit. Have realized that the multi channel sampling control, data compression, data store control function in hard disk. The experiment substantiated, multi channel sampling control unit on FPGA can high speed sample data to a lot of channel; The data processing unit has realized correctly lifting wave transform and hoflrnan coding; The data store control unit can realize 2.4MB/s store speed to hard disk. Every part of function can satisfy the designing requirement. All designs are programmed with VHDL.At the exordium, this paper introduces the task's origin and significance and introduces the research situation on pipeline MFL at home and at abroad. The second chapter explains the structure of FPGA and design flow. The third chapter introduces design of multi channelsampling controller. The fourth chapter introduces lifting wave transform and hoffinan coding and their FPGA realize. The fifth chapter introduces IDE interface and data stores directly to disk hard realizes on FPGA. The conclusion part summarizes the whole work of the paper.