The Design Of The Blind Equalizer On FPGA

In mobile communication and high-speed wireless digital communication, multi-path, the finity of channel bandwidth and faultiness of the channel, lead to the bringing of intersymbol interference(ISI) when data transfer. This is an important factor that degrades the performance of communication. However channel equalization technique can eliminate the ISI and noise, It can also reduces the bit error ratio. This technique developed from fixed-equalization and auto-equalization to adaptive-equalization. Conventional adaptive equalizer generally needs the transmission of a training sequence known at the receiver to make equalizer learn the characteristic of the channel, but this method brings to the transfer delay because of the inserting of training sequence, decreases the transmission rate of useful symbols and increases the system complexity. In addition, sometimes it is impossible to transmit training sequence. However blind equalization technique can depend on only the received data sequence to equalize the channels. So it is widely researched .For Bussgang category blind equalization algorithm, it's quantity of calculate is small and convenient to real-time implement and better performance. So this article uses this category algorithm to implement the blind equalizer.With develop of the Electronic Design Automatic, the integration of field programmable gate array is greatly improved, and it is widely used. So FPGA is the first choice to implement the blind equalizer. This article adopts the design method of top-down, in other word cutting the entire design into small module from top to down, and designing separately, in the end completes the entire design.